| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === This work presents an energy-recycling adiabatic logic for ultra-low energy applications,such as implantable bioelectronics, wireless sensor network, and wearable computing. The AC power supply for adiabatic logic is resonated by an off-chip inductor and parasitic capacitances seen from the power rails. The computation energy is effectively recycled between interleaved DSP logic blocks. The minimum energy consumption can be achieved for several design parameters, such as logic depth, switching activity, threshold voltage, supply voltage, and clock frequency. The proposed adiabatic logic has minimum transistor overhead with full output swing, outperforming the previous state-of-the-art adiabatic circuits. The proposed energy-recycling architecture, adiabatic logic cells, and layout methodology are compatible to current EDA tools for complex VLSI systems. As a proof of concept, a finite impulse response (FIR) filter with proposed adiabatic logic is implemented in 90-nm CMOS process. The FIR filter dissipates 1.96W and achieves a figure of merit of 5.33 nW/MHz/Tap/InBit/CoeffBit at 0.4V supply voltage, yielding the highest energy efficiency compared to prior work. For potential implantable applications, the proposed adiabatic core achieves a 53-70% energy reduction for 87 KHz to 0.42 MHz DSP signal processing at 1V supply voltage compared to static CMOS logic.
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