| Summary: | 博士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === Analog design automation has become one of the most important issue to efficiently achieve design specification in integrated circuit industry. To work on this issue, constraint- driven design generation plays a key role in analog circuit synthesis and layout generation. During circuit synthesis, device models, performance specification and parasitics’ effects consolidate the constraints for exploring the design equation. Yet, to figure out the set of non-linear design equations is complicated and time-consuming. Meanwhile, in layout generation stage, the layout dependent effect (LDE) should be taken into consideration since the performance of analog design is sensitive to physical layout constraints. Traditional layout strategy with manual manipulation requires tremendous time to satisfy specification for sign-off. Moreover, as technology node advances, the complexity of device models and layout constraints is increased as well. The hardship of realization analog circuit on advanced technology node can considerably drop off if the constraints corresponding to design are treated well during synthesis and layout generation.
In this dissertation, we propose an analog design migration framework, which com- prehensively generates analog design from synthesis to layout. The migration strategy is divided into 3 phases: parallel genetic performance exploration for circuit sizing, unified constraint-driven routing for analog layout and rapid prototyping for analog layout migration. To satisfy the migration purpose, both circuit synthesis and layout generation on targeting technology should be satisfied. Our parallel genetic performance exploration analyzes the limitation of a specific technology via genetic algorithm efficiently. Other than examining the corners of device model carefully, genetic algorithm provides a sketch of performance space to explore. Experimental results show that the integration of our genetic performance exploration and probabilistic perturbation achieves both efficiency and accuracy on a radio-frequency distributed amplifier (RFDA) and a folded cascode operational amplifier (Op-Amp) in three different technologies.
The second approach, unified constraint-driven routing, provides an integration concept of generating constraints for industrial analog designs. Most of the layout constraints provided by manufacturing foundries are technology-oriented. However, the design constraints provided by designers are critical as well. We propose an unification of technology and design constraints to perform layout generation. By practicing on an analog functional block of tsmc 40nm SoC design which guarantees to be legalized and satisfies required analog constraints by DRC/LVS and post-layout simulation respectively, the results in wire matching for signal integrity show that the different routing priority generated by our approach can have significant performance impact.
In our last approach of this dissertation, a rapid layout migration for analog circuit is presented. Layout generation for analog design in advanced CMOS technology is challenging due to growing layout constraints and performance specifications. The manufacturing reliability and parasitic effects make the situation more severe. To facilitate the utility of template-based analog layout generation is solving such problem, our migration approach extracts both placement and routing from an existing layout and then implements rapid prototyping to generate multiple results. In addition, the wires in the resulting layout are optimized for better performance. The experimental results demonstrate the possibility on multiple layout migration, such that more than 75% routing of migrated layout is generated with qualified performance. In all, our migration framework achieves the requirement to generate analog design in advanced technologies from synthesis to layout prototypes, and the experimental results have demonstrated the efficiency and accuracy of all three proposed methodologies.
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