| Summary: | 博士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === In modern times, the process technology node has advanced toward small feature size with low power consumption and high operation speed to per the demand on the enormous amount of data computation and communication among individual system-on-chip (SoC). The high-speed interface specifications have evolved toward multi-Gbps data rate as well as low-jitter and energy-efficient (~1pJ/bit) concerns. The transmitter (TX) utilizes spread-spectrum clock generator for the purpose of suppressing the electro-magnetic interference (EMI). The digitally-controlled oscillator (DCO) merged in the all-digital phase-locked loop (ADPLL) combining the triangular profile generator and ΣΔ modulator can build the all-digital spread-spectrum clock generator (SSCG) for the purpose of suppressing the electro-magnetic interference (EMI) with the advantages of the ease of chip integration, small feature size and PVT-tolerant frequency tuning range. For the receiver (RX), the burst-in data needs to be recovered within tens to hundreds of bit-times to save the bandwidth usage so that the big data can be transferred accordingly. By employing the gated-oscillator within the clock and data recovery (CDR) circuit, the recovered data and clock’s phases can be aligned within a few of bit-times to realize fast phase synchronization response.
A low-jitter digitally-controlled oscillator (DCO) with multi-phase differential outputs and good linearity is presented. The DCO is composed of four differential delay cells, and can achieve linear tuning over a wide frequency range. The proposed fully differential delay cell comprises logic cells in standard library and varactors. The dithering scheme employing the ΣΔ modulation can enhance the average DCO’s frequency resolution. The measured rms jitter and pk-pk jitter from 2.5GHz carrier are 2.827ps and 29ps respectively. The power consumption is 6mW from a 1.2V supply. An experimental prototype is designed using 65nm CMOS technology, and the chip area is 156μm×92μm2.
Spread-spectrum clocking method modulates the divider ration to spread the synthesized clock’s center frequency over a small portion on the spectrum. Therefore, the emitted peak energy at the discrete synthesized frequency can be reduced to alleviate the EMI effect. Through an accumulator-based ADPLL using ΣΔ modulator, the proposed all-digital SSCG can be built. The proposed SSCG uses V-by-One display specification for reference. The ADPLL can synthesize the three frequency bands (2376MHz, 740MHz, and 594MHz) accompanied with dividers to cover from 62.5MHz to 2376MHz frequency bands requirement. The SIMULINK behavioral simulation results show that the suppressed EMI amounts are 19.95dB, 13.99dB, and 14.65dB for the 2376MHz, 740MHz, and 594MHz frequency, respectively. The synthesized area and power of the SSCG’s digital components are 4230μm2 and 0.72mW from 0.9V supply in the 40nm CMOS process node. The band-selection DCO merged in this SSCG occupies area of 1961μm2 and dissipates 3.34mW from 0.9V supply in the 28nm CMOS process node.
A burst mode clock and data recovery (BMCDR) circuit for 10Gbps passive optical network (10G-PON) is presented. The design issues including the prevention of the gated-oscillator’s frequency mismatch, the jitter tolerance ability, the short lock-in time and energy-efficient concern have been addressed. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. The lock detector can guarantee the frequency accuracy of 0.01875% in the frequency initialization locked state. The proposed selectively gating voltage controlled oscillator (SGVCO) can pass the input data edge to the proper gating stage of the SGVCO that has the closest transition phases with it. When the SGVCO is settled, the input data transition edges are aligned with the SGVCO’s output phases at 1/5-rate of input data. After data gating process, the proposed BMCDR reconfigures as a 2nd-order conventional CDR loop to suppress input stressed data without retarding the locking behavior. By incorporating selectively gating VCO (SGVCO), the BMCDR can operate at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UIpp jitter stressed input data at 10Gbps, the recovered clock jitter at 2GHz is 2.94psrms. The prototype is fabricated using 55nm CMOS technology. The core area is 0.03mm2 only. It dissipates 12.4mW from 1V supply.
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