| Summary: | 博士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === This dissertation investigates the BCH codes from algorithms to architecture designs and VLSI circuit implementations for various design targets of NAND Flash memory application.
In order to meet the varying requirement of error correction capability, the multi-mode error correcting capability feature is very crucial for BCH codec in NAND Flash memory. By exploiting the properties of minimal polynomial, the proposed minimal-polynomial-based architectures for encoder, syndrome calculator and Chien search logic of BCH codes can not only support multiple error correcting capabilities but also preserve high area-efficiency. In our MPCN-based BCH codec designs with arbitrary error correcting capability, the test chip supports t = 1 ~ 24 bits while the other design supports enhanced t = 60 ~ 84 bits. These designs can respectively achieve 1.33 Gb/s and 1.60 Gb/s at the cost of 73.0K and 168.6K gate-count from the implementation results under 65 nm CMOS technology.
For most applications of NAND Flash memory, the BCH decoder is widely designed as 3-stage pipelined structure. By using composite field divider with BM algorithm and dynamically assigning the clock cycles of each iteration, the proposed area-efficient KES with echelon scheduling successfully reduces the usage of hardware components without performance degradation. According to the implementation results, the single-mode (9200, 8192; 72) design can provide 3.08 Gb/s throughput with 147.8K gate-count from the post-APR simulation result. Based on the single-mode design, the revised test chip is able to support multi-mode t=24, 48, 60, 72 error correcting capability with reduced 124.7K gate-count based on the implementation results under 90 nm CMOS technology. Moreover, it is proved that all presented BCH codec designs meet the performance target of industry standard.
For the extremely high throughput demand application such as the solid-state drives (SSD), the proposed Truncated Simplified Inversion-less Berlekamp-Massey (TSiBM) algorithm for low-latency key equation solver achieves significant hardware
reduction as compared with the previous works and also is able to efficiently serve the computation within the proposed multi-channel BCH decoder. The proposed KES design with TSiBM algorithm requires 243.3K gate-count achieving 41.4% reduction compared with SiBM algorithm. In the proposed scenario of 8-channel BCH decoder, the average gate-count of BCH decoder per channel is 264.3K, resulting in 20.5% reduction as compared with the traditional 3-stage pipelined structure.
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