A Fast Integrated Placement and Routing Framework for Floorplan Prototyping
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === Routing congestion has become a critical issue in modern custom digital design as the number of transistors increased. However, many researches are dedicated in solving this problem in placement stage or even later in routing stage. Yet, according to recent...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92192854899017034453 |