Low Power CMOS Ultra-Wide-Band and Millimeter-Wave Low Noise Amplifiers Analysis and Design

• Main Authors: Lin, Ching-Shiang, 林敬翔
• Other Authors: Guo, Jyh-Chyurn
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/3b7p66

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === In this thesis, low power low noise amplifier (LNA) design and fabrication have been accomplished using 0.18 m and 90 nm RF CMOS processes, for potential applications in ultra-wide band (UWB) and millimeter wave wireless receivers. The primary achievements contain three circuit chips, such as two UWB LNA and one V-band LNA, employing different circuit topologies. The first UWB LNA was built with a two-stage cascade topology, incorporating resistive shunt-shunt feedback for wideband input matching, forward body-biasing (FBB) scheme for low voltage and low power, inter-stage series LC resonator for ac current amplification and power gain boost, and inductive shunt peaking technique for bandwidth extension. An extensive work of equivalent circuit analysis has been conducted for input and output matching, power gain, and high frequency noise in UWB LNA design. Analytical models can be derived to simulate the performance parameters, such as input and output return loss, S11 and S22, power gain S21, and noise figure, responsible for the key features of major concern in UWB LNA design. The accuracy of our analytical model was justified by a good match with ADS simulation. Note that, the derived analytical model in an explicit form containing physical parameters, without need of numerical solver, can facilitate the simulation efficiency and guide the performance optimization or diagnosis. A performance benchmark indicates that this UWB LNA using a cascade topology, demonstrates the advantage of much lower VDD, lower power dissipation, higher linearity (IIP3) and comparable noise figure, but the drawback of lower S21 at higher frequency and reduced bandwidth for S21 > 10dB, due to abnormally large Rfb caused by a mistake in resistors layout. A layout correction to meet the target Rfb should offer right solution to cover the performance. Finally, the third LNA chip aimed for application in V-band receiver was design and fabricated in tsmc 90nm low power RF CMOS. This V-band LNA was implemented by a distributed amplifier containing 3-stage CS amplifiers, with inductive source degeneration at the first stage, inter-stage transmission lines (TML) for broadband matching, without need of spiral inductors, and again FBB technique for low voltage and low power. An extensive simulation has been conducted, using 3D EM simulation like Ansoft HFSS, to realize TML design aimed for V-band operation. Afterwards, the S-parameters achieved from HFSS were adopted as the design target for ADS to build TML model, which can facilitate circuit simulation and optimization. The measured chip performance indicates the advantage of higher gain S21 and wider bandwidth for S21 > 10dB than post-layout simulation. There is a shift of the minimum S11 but the input matching keeps good in required bandwidth. Higher noise appears as the primary drawback and more effort is required in the future work for an effective improvement.