Optimization Methodologies of Using On-Chip Hardware Process Monitors for Speed Binning
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === In this work, an optimization methodologies of using on-chip hardware process monitors for speed binning is proposed. A flow of composed of SDF-modifying technique and model-fitting framework is used to generate the simulated data and analysis where and how...
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/34681536648402676057 |
| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === In this work, an optimization methodologies of using on-chip hardware process monitors for speed binning is proposed. A flow of composed of SDF-modifying technique and model-fitting framework is used to generate the simulated data and analysis where and how many should we place hardware process monitors. The proposed guide line for on-chip hardware process monitors placement shows better
efficiency than greedy method. The mean error and maximum error is reduced over 50% in different parameter of process variation. A comparison of different method of speed binning is also presented.
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