Ultra-Low Voltage All Digitally Controlled Linear Voltage Regulator Design for Event-Driven Energy-Efficiency Sensing Platform
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === In this thesis, two digitally controlled linear voltage regulators are proposed for event-driven energy-efficiency sensing platform. Both digitally controlled linear voltage regulators are implemented on TSMC 65-nm low-power bulk CMOS technology and designe...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22310366975755448024 |
| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === In this thesis, two digitally controlled linear voltage regulators are proposed for event-driven energy-efficiency sensing platform. Both digitally controlled linear voltage regulators are implemented on TSMC 65-nm low-power bulk CMOS technology and designed for near-/sub- threshold operations.
The first digitally controlled linear voltage regulator includes a digital error detector (DED), which is the replacement of the analog error amplifier. A novel Process-Voltage-Temperature (PVT) –aware design is implemented to mitigate environmental variations and to guarantee the resolution of linear voltage regulator.
In the second digitally controlled linear voltage regulator, a comparator-based error detector is proposed to replace analog error amplifier. Two methods are introduced to reduce self-generated output ripple by adjusting the PMOS strength for PVT and load variations.
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