| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === Radio-Frequency identification (RFID) system is a well-developed technique and is everywhere is our daily life, such as campus IC cards, access cards, electronic toll collection, etc. Efforts have been made mainly on a RFID tag IC design since the size of a tag directly determines the variety of RFID applications. Current RFID tag has large physical size due to the off-chip antenna, which limits the RFID applications because a tag cannot be mounted on objects smaller than itself. In this thesis, a downlink/uplink operating frequency of 60/24 GHz is used in order to reduce the antenna size. Since the proposed tag is passive, it requires a rectifier which converts RF power collected from surroundings to dc output supply voltage. A design of a robust rectifier becomes the most important task needed to be accomplished because as the frequency moves higher, the sensitivity of a RFID tag decreases due to the inevitable parasitic capacitance which impact the rectifier’s performance significantly. To overcome the parasitic effects, this thesis proposes an In-Phase Gate-Boosting Rectifier (IGR) which is a new circuit technique. The implemented IC achieves a state-of-the-art -7 dBm sensitivity with a peak power conversion efficiency of 20.65% at 7 dBm input power in the millimeter-wave rectifier circuit design domain.
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