| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === Nowadays, many integrated circuits (ICs) of electrical products are fabricated in a high-voltage process. For example, driver ICs for various display panels, power management ICs and automotive ICs are commonly fabricated in a HV process. In a high-voltage process, HV transistors are born with complicated structure for the increase of the operating range and breakdown voltage, and that makes electrostatic discharge (ESD) protection design more difficult and challenging.
In ESD protection design for HV applications, it is common to use lateral diffused MOS (LDMOS) as an ESD protection device. LDMOS is a general HV MOS, and its ESD robustness is worse than a low-voltage device’s. It has to enlarge LDMOS, and be aware of uniformity for ESD protection.
In ESD protection design for HV applications, holding voltage of a device is an important factor. When holding voltage of a device is lower than supply voltage, it is possible that latchup occurs in applications. In some noisy environment, this factor should be paid more attention.
Low-voltage devices are proved for good ESD robustness per area, and the devices can be enhanced by many methods. Stacking makes the devices’ trigger voltage and holding voltage increase so that the devices meet the conditions for HV applications. For area and ESD robustness concerns, stacking can be one of the best ways.
In this thesis, stacks for ESD protection are implemented and verified, and it is discussed for the problems and improvement. Stacked configuration in different shapes is also examined. Increasing turn-on speed by replacing with other devices will be discussed.
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