| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === High k materials such as Hafnium dioxide are being used as next generation CMOS gate dielectric. Conventional SiO2 or SiON dielectric has its limits in CMOS scaling: inevitable leakage current for thinner oxide. With the help of high k materials, the gate oxide now can grow thicker to reduce leakage current without increasing electrical oxide thickness. In order to achieve adequate breakdown time, a thin and native layer of SiOx is always needed. However, many well known problems need further attention: Negative Bias Temperature Instability (NBTI) due to the imperfect interface of SiOx and HfOx; Positive Bias Temperature Instability (PBTI) due to the intrinsic oxide traps. Therefore, it is important to understand the properties of these traps, and Random Telegraphic Noise (RTN) is a powerful method to analyze it.
First, in this work, we have developed a method to extract the trap position and energy level by measuring the capture and emission time of RTN signals. Through these information, we can analyze the damage caused by BTI stress, in which a leakage filament was formed. Both Inversion Mode RTN and Accumulation Mode RTN will be performed after PBTI and NBTI. Although the Accumulation Mode RTN has rarely been discussed, we have also demonstrated its importance to include the measurement of accumulation mode. Our results shows, by combing Inversion Mode RTN and Accumulation Mode RTN, a comprehensive detection window can be detected.
Next, from the concept of the leakage filament, it raised our great interest in finding the leakage path that leads to the final breakdown. We traced traps location after each BTI stress until breakdown, and the entire breakdown path can be revealed. In this thesis, we have performed both Constant Voltage Stress and Constant Current Stress for both nMOSFET and pMOSFET. We presented that two types of breakdown path were observed: Spindle-liked breakdown and Snaked-liked breakdown path. A new concept to explain these various results: Energy Flux. Generally, nMOSFETs have larger current but lower carrier energy compared with pMOSFETs; CCS has more progress breakdown and damage in oxide as a result of the decreasing power dispersion.
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