A 2.2mW 5GHz All-Digital Phased-Locked Loop for Analog Multi-Tone Transceivers
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === Nowadays, the all-digital PLL is a vital block of high speed serial link applications. The proposed low power and high speed ADPLL has been implemented and integrated with analog multi-tone (AMT) transceiver. The ADPLL design specification is based on the w...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78549426812636539388 |