| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 103 === With the advances in modern semiconductor technologies, leakage power has become an issue of concern. Many researches have proposed hardware and software techniques to reduce leakage energy. Power gating is an effective technique that turns idle components into low-power mode to reduce leakage energy at the hardware level. However, the distribution of functional unit usage is often scattered within a program, and it is unfavorable to apply power gating to functional units, the idle time period of which is fragmented into short idle fragments. In this thesis we attempt to cluster the distribution of functional unit usage within loops so as to extend the idle durations of functional units and thereby to increase the opportunity for energy saving. We present an energy-aware loop transformation framework for a compiler to generate distributed loops on leakage energy considerations. Our framework provides a binary quadratic programming (BQP) model that attempts to divide a loop body into several loops, with each loop having different functional unit requirements. We have incorporated our proposed framework into the GNU compiler collection (GCC) and simulated performance and energy consumption using sim-panalyzer. The experimental results demonstrate that our framework was effective in reducing the energy consumption of functional units without significant loss of performance.
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