| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 103 === The Memory-Wall causes the overwhelming bottleneck in computer performance. An efficient memory hierarchy is designed to alleviate the memory latency. The memory usage and operating system are closely related, but there is a growing gap between architectural research and OS research. In this thesis, we propose a novel analysis framework to connect the OS behavior and the hardware architecture based on full-system simulation so that we can explore the impact of system behavior on memory hierarchy. We proposed a lightweight event catcher to trace the system event. By combining the system event with hardware information, which is obtained from hardware monitor in the QEMU, we can not only obtain the full-system trace but also these important OS kernel events that are correctly interleaved in the memory trace. The advantages of our approach includes a detailed memory evaluation study can be performed from perspective of operating system events. To demonstrate our platform, we analyzed the memory system behavior with some new observations in spatial domain and temporal domain. According to the observation results, we provide several recommendations for the adjustment in the future design.
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