Design and Implementation of an Efficient Progressive Radiance Estimation Engine for Progressive Photon Mapping
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 103 === In this work, a progressive radiance estimation engine (PREE) hardware architecture is proposed to accelerate the processing of the progressive photon mapping. The proposed PREE architecture consists of four progressive radiance estimation units (PREUs), flux...
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| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/n44wx6 |
| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 103 === In this work, a progressive radiance estimation engine (PREE) hardware architecture is proposed to accelerate the processing of the progressive photon mapping. The proposed PREE architecture consists of four progressive radiance estimation units (PREUs), flux correction controller (FCC) and radiance evaluation controller (REC). PREU can share hardware resource for flux correction and radiance evaluation and adopts pipeline to accelerate the radiance estimation computation. Through FCC and REC, the data can be efficiently dispatched to gain the better parallel computing and prevent data dependency with four PREUs, respectively. The proposed PREE architecture is implemented in TSMC 90 nm CMOS process with the core area of 1.78 mm2. According to the post-layout simulation results, the proposed PREE architecture implementation can achieve the hit-point rate of 496 MHpO/s and consumes the power by 184 mW at 125 MHz.
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