| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 103 === The buck DC-DC Converter is widely used in various electronic devices. When designing a digital buck DC-DC converter, the digital pulsewidth modulator (DPWM) is definitely one of the key building blocks of the entire buck converter. A time-adder-based DPWM is proposed in this thesis. The proposed DPWM features high-resolution, low hardware cost and easy-to-implement in either a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) as compared to most state-of-the-art DPWMs.
The technology of proposed time-adder-based pulsewidth modulation is implemented on Altera DE0 FPGA board and is also integrated for a buck DC-DC converter application. The experimental results show that the regulated output voltage ranges from 0.6V to 2.5V and the maximum load current is 1A, when the supply voltage of proposed buck converter ranges from 1.8V to 3.3V. While the regulated output voltage is set to 1.8V with a 3.3V supply voltage, the transient response time and the undershoot voltage are respectively 254μs and 160mV under a light-to-heavy loading condition, i.e. the load current changes from 100mA to 1A; The transient response time and the overshoot voltage are respectively 266μs and 140mV under a heavy-to-light loading condition. Meanwhile, the output ripple is less than 100mV and the efficiency is up tp 90.9% under all operating conditions.
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