Design of Fast-Locking PLL Combined with DLL for 1.8 GHz Wireless Communication System
碩士 === 國立成功大學 === 電機工程學系 === 103
Main Authors: | Ting-LinWu, 吳廷霖 |
---|---|
Other Authors: | Tzuen-Hsi Huang |
Format: | Others |
Language: | zh-TW |
Published: |
2015
|
Online Access: | http://ndltd.ncl.edu.tw/handle/08165756873577048583 |
Similar Items
-
5.5GHz Fast Lock All Digital PLL Design
by: Chia-Chun - Lin, et al.
Published: (2016) -
Design and Application of CMOS PLL/DLL
by: June-Ming Hsu, et al.
Published: (1999) -
Implementation and Application of CMOS DLL/PLL
by: Guang-Kaai Dehng, et al.
Published: (2001) -
A 1.8V, 2.4-GHz CMOS PLL-BASED FREQUENCY SYNTHESIZER FOR WIRELESS COMMUNICATIONS SYSTEMS
by: Kuen-Yu Li, et al.
Published: (2002) -
The Realization of Clock Recovery Circuit with DLL and PLL
by: Chua-hua Lee, et al.
Published: (1999)