| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 103 === This thesis presents an algorithm design and hardware implementation for 18-band quasi-class-2 ANSI S1.111/3 octave filterbank, which achieves low computational complexity and group delay. The develoging technique of this thesis is summarized as follows: 1) integrate a prototype low-pass filter and discrete cosine transform modulation to realize a 9-band uniform filterbank; 2)replace all z-1 elements of FIR by all-pass filters to abtain an non-uniform filterbank, which meet the band 31-39 of ANSI spec; 3)apply multi-rate structure to filter band 22-30, which use the same filterbank structure with band 31-39 but alternate the sampling rate of input signal; 4)reduce the computational complexity by coefficient repeatability and improvement of DCT length “M” selection. The proposed analysis filter bank was implemented at FPGA, the wordlength of each block was analyzed separately to lower the hardware cost, and applied pipelined scheduling to reduce operating cycle. Integrate the CPU of FPGA with our circuit to verify the accuracy. Compare with the researchs of recent years, this thesis present a good performance of group delay, computation complexity and real-time clock rate, which is suitable for the application of digital hearing aids.
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