Study and Analysis of Multi-Processor Architecture for Various Levels Parallelism

• Main Authors: Ding-YuanLin, 林鼎原
• Other Authors: Jer-Min Jou
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/38337405874223234184

碩士 === 國立成功大學 === 電機工程學系 === 103 === Traditional single-core processors use out-of-order execution, superscalar, speculative execution and other techniques to improve performance. Clock speed is not the answer when it comes to energy consumption and heat dissipation. Limited by memory access latency and inherent parallelism of the program instructions, known as instruction level parallelism. Modern processors use multithreading techniques, which allows us to perform concurrent processing, and find the potential parallelism between threads (Thread level Parallelism), even if there’s only one single-core processor. In consideration of energy efficiency, the trend of processor design toward single chip multi-processor. In this thesis, we study and analysis of multi-processor architecture for various levels parallelism. By using gem5 which is a cycle accurate simulator simulates pipeline stages cycle by cycle, we can configure and simulate the target platform as soon as possible. We have shown that the performance of MiBench applications running with out-of-order processor is much faster than those running with in-order and non-pipelined processors. In addition, we also study and analysis task level control processor hardware architecture and its behavior. The control processor keeps tacking dependencies between tasks, automatically extracts parallelism among coarse-grain tasks and schedules them for execution on underlying processors. In the end, we have made a comparison between instruction and task level processors architecture.