| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 103 === This thesis presents a high effective resolution bandwidth (ERBW) high speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with differential input signals. This ADC is designed as the sub-ADC that constructs a time-interleaved ADC. Therefore, the range of ERBW is much considered.
In addition, parallel signal paths are used in the control logic circuit to decrease the delay time of producing triggering signals, which enlarges the room for speeding up the sampling rate of the ADC compared with the conventional design.
Chip sarf2_32 that was fabricated under TSMC 90nm RF process was measured 6.7 bits at low frequency while it was measured 3.8 bits at high frequency. As the input frequency goes higher, the ADC''s performance gets worse. This problem can be solved with the use of cross-couple MOS in the sample and hold circuit. The measured power consumption is 4.5mW, and the FOM is 321fJ/conversion-step.
Fabricated under TSMC 90nm GUTM process, chip sarf2_33 was measured 5.6 bits at low frequency and it was measured around 4.8 bits at high frequency. The results of measurement are similar to that of FF corner simulation. The measured power consumption is 5.61mW, and the FOM is 692fJ/conversion-step.
Source followers are used at the input as input buffers for sarf2_34. Above 7 bits of ENOB were simulated under SS, TT, and FF corner from low frequency to high frequency. The simulated power consumption is 5.8mW, and the FOM is 206fJ/conversion-step. This chip has been taped out under TSMC 90nm GUTM process.
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