A Study on the Reliability of α-Si:H TFTs Stressed by Different DC Voltages and White Light Illumnance

• Main Authors: Jing-Syue Lin, 林敬學
• Other Authors: 劉漢文
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/25208301059699459473

碩士 === 國立中興大學 === 光電工程研究所 === 103 === Amorphous silicon thin film transistors (a-Si TFTs) is widely used in various electronic products. With the mature skills, more less process steps and low cost, but if we compare the a-Si TFT with low-temperature polycrystalline silicon thin film transistors (LTPS TFTs), a-Si TFTs have low mobility and bad reliability. Therefore, it is important to investigate the reliability of a-Si TFTs in drive circuit. The main propose of this study was to investigate the a-Si TFTs’s reliability when it stressed by different DC voltages and white light illumnance. After a-Si TFTs stressed by white light illumnance, weak bond of silicon with silicon bonded or silicon with hydrogen bonded may be broken. It produced the dangling bond and threshold voltage had a rising situation. When a-Si TFTs stressed by positive gate bias, electrons were attracted by positive bias in the active layer. So the defect mechanism is electron trapping. Threshold voltage increased because the main transmission carrier is electrons. Next we fix two kind of stressed condition. First, a-Si TFTs stressed by white light illumnance before stressed by DC voltages, we found TFTs had the recover phenomenon；Second, a-Si TFTs stressed by DC voltages before stressed by white light illumnance. It has recover phenomenon, too. At last, a-Si TFTs stressed by white light illumnance and DC voltages at the same time. The threshold voltage has the largest degradation. Because illumination produced electrons and the positive bias attracted negative charges ,it caused more electrons captured by the traps. It was found that the defect occurs mainly in the part of the junction between active layer and passivation layer. 　a-Si TFTs stressed by white light illumnance and DC voltages at the same time　had the largest degradation, so we changed different illumination and voltage conditions to experiment. When fixed the illumnance , the threshold voltage and on region current has larger degradation with the gate bias get larger；When fixed the gate bias, the threshold voltage and on region current has larger degradation with the illumnance get larger. Stressed by white light illumnance and DC voltages at the same time produced current in the active layer is larger than the gate bias. The current in the active layer is larger with the gate bias. Use the power law for the curve fitting , when white light illumnance or DC voltage increased at a-Si TFTs stressed by white light illumnance and DC voltages at the same time , the charge trapping will be more obvious.