Electrical performance and micro-loading effect of n-type FinFETs with temperature stress

• Main Authors: Jian- Liang Lin, 林建良
• Other Authors: Mu-Chun Wang
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/85964889347772986410

碩士 === 明新科技大學 === 電子工程系碩士班 === 103 === For the traditional CMOS transistors with planar form, these devices have been applied for a long time in semiconductor industry. Due to the need of the IC marketing, the shrinkage of device feature is a major trend, but the process development also faces lots of issues and challenge. Furthermore, the decrease of the power supply is the other urgent need to reduce the power consumption in IC operation. In the meantime, the physical limitation in lithography is gradually approaching, therefore, the novel replacement technologies must be delivered soon. In this study, one set of 90nm lithographical masks with hard masks were employed to fabricate the FinFET devices through the adjustment of exposure energy in lithography and the control of parameters of dry etch process. However, the micro-loading effect after dry etch in multiple-channel n-type FinFET devices was observed with the analysis of I-V characteristics. The residue height (H) in spacing between both channels was around 2.4nm assuming the inner spacing owning the uniform H. After the temperature stress, the surface integrity at the vertical sides of the channel width was demonstrated. Because of the application of the plasma etch process, the optimal etch recipe seems not to be controlled well. Thus, the deviation of channel mobility with the increase of stress temperature in each tested device is distinct. Besides the different channel-length devices to expose the influence of exposure energy in lithography and indirectly impact the whole device performance, the adjustment of VT implant energy (10KeV and 6KeV) with boron species was guided into the investigation of electrical device performance.