Mixed-Mode Integrated Circuit Design

• Main Authors: Li,Yu-Sheng, 李育陞
• Other Authors: Wu,Chang-Hsi
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/94079833397380312626

碩士 === 龍華科技大學 === 電子工程系碩士班 === 103 === This thesis introduces mixed-mode circuit designs which are related to the operational amplifiers (OPAs). In these designs, required specifications are firstly needed to know since different design of operation frequency, gain and power consumption of OPA is required to different application. An OPA with larger unit-gain frequency under lower power dissipation is more popular. Conversion between analog and digital signals and reducing the impact of CMOS noise on signals are discussed in this thesis. The designed circuits include analog front-end circuit of bio-medical, chaos generator for encryption and decryption, 5.2G Hz frequency synthesizer and 10-bits SAR analog to digital converter (ADC). These are the hot topics in the electronics industry market in recent years. In the second chapter, analyses of various types of OPAs and switches used in mixed-mode circuits are described for fast analysis in the design procedure. These contents will be corresponding to the later chapters. Chapter three describes mainly on the analog front-end signal processing of bio-medical EMG, ECG and EEG. The chopper stabilization technology is used in the amplifier to enhance the anti-noise ability. In the fourth chapter, chaotic dynamic signal generator is designed base on the Lorenz-Stenflo system. It can be used to construct the encryption and decryption systems. Chapter five describes the frequency synthesizer, in which feedback loop of frequency and phase for a controlled voltage is applied to the 5.2G Hz VCO for upgrading stability and reducing phase noise. In the sixth chapter, a 10 bits analog-to-digital converter is designed using successive approximation technology with error induced by the capacitance delay of charge injection. All the circuits in the thesis are designed based on the TSMC 0.18μm or 0.35μm processes.