A Capacitor-Less Low Dropout Regulator with IC Package Effect
碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 103 === This paper presents a capacitor-less low-dropout linear regulator. Our design considers the parasitic effects of various IC packages. To suffice the SoC target, the designed low-dropout regulator (LDO) only uses the monolithic capacitor to realize the frequ...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/76412835135022086145 |
| Summary: | 碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 103 === This paper presents a capacitor-less low-dropout linear regulator. Our design considers the parasitic effects of various IC packages. To suffice the SoC target, the designed low-dropout regulator (LDO) only uses the monolithic capacitor to realize the frequency compensation. Combining the parasitic effects of current major power management IC package (namely FOWLP (Fan Out Wafer Level Package), a-S^3 with wirebond and a-S^3 with Cu pillar) to design the whole circuit.
The proposed design is fabricated in the TSMC 0.18um 1-poly 6-metal CMOS process. The input voltage of this LDO is 1.8V and current is within 10mA-100mA. It is from the output of a converter. According to the HSPICE simulation results, the LDO can output a stable 1.5 V. The ripple voltage can be reduced from original 5mV to 800μV. With the consideration of three different IC package models, the simulated output voltage is within 1.495V and 1.5V with driving current of 10mA to 100mA.
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