Efficient video coding methods and DSP realization for H.264/AVC and H.265/HEVC standards

• Main Authors: Chi-Wei Tung, 董棋偉
• Other Authors: Chou-Chen Wang
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/22843274798507312579

博士 === 義守大學 === 電子工程學系 === 103 === With the rapid development of digital multimedia service, full high definition (FHD) and ultrahigh definition (UHD) resolution is more and more popular in the multimedia service. The up-to-date video coding standards including H.264/MPEG-4 Advance Video Coding (AVC) and H.265/MPEG-H High Efficiency Video Coding (HEVC) could support FHD and UHD resolution video applications, respectively. However, H.264/AVC and H.265/HEVC standards require enormously computational complexity in encoding process which results from the time-consuming works of intra/inter prediction and transform/quantization (DCT/Q) modules. Therefore, it will be hard to realize the real-time applications. In order to reduce the computational complexity of H.264/AVC and H.265/HEVC, we propose some efficient video coding methods including fast intra prediction module, early terminated DCT/Q module and efficient rate control module, respectively. In this dissertation, we propose some efficient coding methods for H.264/AVC standard to speed up the encoding process. Firstly, we develop a fast intra mode decision algorithm for H.264/AVC which takes advantage of the mode correlation between MBs/blocks with a suitable threshold according to interblock correlation. The proposed fast decision algorithm can provide a good tradeoff between the R-D performance and the computational complexity. Secondly, a more efficient and fast algorithm is proposed in DCT/Q module using early detecting all zero blocks (AZB) which combines Parseval theorem and successive elimination algorithm (SEA). The simulation results show that the proposed algorithm achieves approximately a 12%~22% computational saving when compared to the existing methods. Finally, in order to finish real-time video streaming scenario, a more efficient rate control scheme is proposed. A fast and best selection of initial QP is first proposed in the GOP layer rate control. Then, an improved MAD prediction model and overhead bits prediction method is adopted in the MB layer rate control. The simulation results show the proposed scheme improves the number of frame skipped and reduces the quality deviations of initial frames by choosing the best initial QP. In addition, we also propose an efficient coding method for H.265/HEVC standard in this dissertation. To reduce the computational burden of H.265/HEVC encoder, an early transform unit (TU) decision algorithm (ETDA) is adopted to prune the residual quadtree (RQT) at early stage based on the number of nonzero DCT coefficients (called NNZ-EDTA). In order to further improve the performance of NNZ-ETDA, we propose an adaptive RQT-depth decision for NNZ-ETDA (ARD-NNZ-ETDA) by exploiting the characteristics of high temporal-spatial correlation. An adaptive depth of RQT is employed to the NNZ-ETDA to further reduce the computational load of TU module. Simulation results show that the proposed method can achieve time improving ratio (TIR) about 61.26%~81.48% when compared to the H.265/HEVC test model 8.1 (HM 8.1) with insignificant loss of image quality. Compared with the existing NNZ-ETDA, the proposed method can further achieve an average TIR about 8.29%~17.92%. The latest generation of digital signal processors (DSPs) can support very flexible codec at a relative low cost. Therefore, in order to further achieve the DSP realization for the proposed efficient H.264/AVC and H.265/HEVC standards, we embed the codec on the ADSP-BF548. To achieve the fast requirement of embedded H.264/AVC and H.265/HEVC based on ADSP-BF548, we propose a highly efficient memory assignment (HEMA) technique to modify the allocated internal memory and optimize the source codes. Firstly, the HEMA analyzes the complexity of encoding modules for H.264/AVC and H.265/HEVC, and then we re-allocate the reference frame from L3 DDR-RAM to L2 SRAM to increase the speed of execution of motion estimation (ME) module and re-allocate the function of consuming module from L3 DDR-RAM to L1 SRAM. Finally, we make use of direct memory access (DMA) and the default function of ADSP-BF548 to carry out program steps. In addition, the parallelism between algorithm execution and data movement has been fully exploited using DMA. Experimental results demonstrate that the decoding rate can reach above 30 fps to acheve real-time applications.