Study of the recognition rate and weight retention in CMOS hardware perceptrons

• Main Authors: Tsung-Sian Wu, 吳宗憲
• Other Authors: Syang-Ywan Jeng
• Format: Others
• Language: zh-TW
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/824u86

碩士 === 中原大學 === 電子工程研究所 === 103 === The artificial neural network (ANN) simulates the operation of the human brain which dominates the signal handing. With the advancement of technology and living standard, ANN has been widely used in various industries. Hardware portability is also becoming indispensable nowadays. In this thesis we use the 4*3 NOI synapse array silicon to implement neural network circuit. And supervised learning algorithm is accomplished by tester machine for neural network application. According to the selected algorithm, the tester controls the NOI synapse array operations. Weight updating is done by programming and erasing mechanism and also determines the performances of neural network system. In order to enhancing the recognition rate and data retention of the existing neural chip, we propose a novel learning method which is called enhancement learning. Different from the traditional perceptron algorithm, after the convergence, the initial judgment level of the perceptron algorithms will be enhanced to a marginal level, which is equivalent to a tolerant region during recognition. In comparison of the conventional for perceptron learning, the enhancement learning can achieve better data retention and recognition. The pattern recognition rate is evaluated by random shading. The enhancement learning can significantly improve the hardware neural network system whose recognition rate increases from 78.81% to 94.44%. In addition, its useful life can be increased from 200 seconds to 10,000 seconds at 150 ℃ high-temperature baking. Finally, the training data of hardware experiment has also been compared with our software simulation for its recognition rate.