| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 103 === This thesis presents a calibration circuit of power-line interference elimination for low-power analog front-end circuits of an ECG acquisition system. The notch-frequency will be altered by PVT variation and aging, and it should be tuned by calibration circuits to fixed the notched frequency approached to the power-line frequency. The notch-frequency tuning circuit can be integrated into analog front-end circuits of an ECG acquisition system. The ECG acquisition system contains a preamplifier, a low-pass filter, a notch filter, a post-amplifier, and an analog-to-digital converter. In order to calibrate the notch-frequency shifting, a digital calibration circuit is proposed. The overall circuits with core area of 2.66 mm2 have been implemented in a TSMC 0.18 μm 1P6M standard CMOS process technology. In order to achieve a low-voltage and low-power system, this system is operated in weak inversion at 1-V supply voltage with the total power consumption of 850 nW.
|
|---|
