High Scalability FPGA-based hardware accelerator for data-intensive computation.

• Main Authors: Dai-Hua Li, 李岱樺
• Other Authors: Ching-Che Chung
• Format: Others
• Language: en_US
• Published: 2015
• Online Access: http://ndltd.ncl.edu.tw/handle/d55m2s

碩士 === 國立中正大學 === 資訊工程研究所 === 103 === Nowadays, the smart phones, web systems, and wireless sensors are enabled to connect the Internet, and response to user in real time. Therefore, we are living in the internet of things (IoT) era with big data generation. The “4Vs” characteristics of big data such as variety, volume, velocity, and value make them difficultly to be handled. The personal computer is hard to deal with big data, because the capacity of memories and storage devices is not enough and the limited processing rate of the CPU. Therefore, the distributed file system and cloud computing have become popular. Both of them can compute in parallel and share the data of disks. Moreover, the hardware accelerator is suited for data-intensive computation, and the function units of hardware accelerator are processed in parallel. Graphic processing units (GPUs) and field programmable gate arrays (FPGAs) are potential hardware accelerators. K-means clustering algorithm is one of the data mining techniques. K-means is used to find the relation between the data, or for image processing. Therefore, in this thesis we implement k-means clustering algorithm to analyze the dataset. The FPGA-based hardware accelerators that communicate with computer through switch are proposed. The computer wraps data into packets to FPGA, and it receives data after the FPGAs are finished computation. In addition, the host computer is employed as the master to manage data and dispatch jobs, and the FPGAs are focused on accelerating data computation. Finally, the proposed system performance is compared with the benchmark execution time.