| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 102 === With the progress of chip manufacturing processing, fabricating the 32 nm or even 22 nm patterns using a 193 nm stepper, dramatically increases the difficulty of standard cell layout design. Therefore, the layout patterns of chip designs tend to be more regular in order to decrease the variation of fabricated pattern resulting from lithography.
In this thesis, the layout style called “Back End of Line-Limited Regular Fabric” is used to design standard cells whose layout patterns will be more friendly for manufacturing. Followed by that, we build up a standard cell library based on this style. Experimenting with ITC99 benchmarks, the circuits synthesized based on our cell library have similar power consumption to that of the circuits synthesized based on a commercial standard cell library. However, ours use more than two times area and have much more delay on the longest path.
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