Study and Implementation of a Three-Level Zero-Voltage Switching Converter with Efficiency Improvement

• Main Authors: Jian-Ting Liao, 廖健廷
• Other Authors: Bor-Ren Lin
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/18174768644836930309

碩士 === 國立雲林科技大學 === 電機工程系 === 102 === This paper presents a three-level zero-voltage DC-DC converter with phase-shift pulse-width modulation (PWM) control for high input voltage application. In the proposed converter, power switches can be achievedat zero voltage switching (ZVS). The circuit architecture of the proposed converter includes a three-level circuit with phase-shift PWM schemein the primary side and an auxiliary passive snubber in the secondary side in order to reducethe circulating current and improve circuit efficiency. First, the three-level circuit can reduce the voltage stress of power switches at one-half of input voltage. The phase shift PWM scheme is adopted to achieve power switches turn-on at ZVS by using the switch junction capacitance and transformer leakage inductance. The symmetric PWM scheme can improve transformer flux variation and transformer efficiency.Secondly, two center-tapped rectifiers are parallel to share the load current for low voltage and high load current applications. The auxiliary passive snubber is added at the secondary side to reduce the circulating current and improve the circuit efficiency. In this thesis, the analysis and design example of the proposed converter will discuss in detail.Finally, the prototype circuit was set up and the circuit performance will be verified by the measurement results.