| Summary: | 碩士 === 國立雲林科技大學 === 電子工程系 === 102 === A high-efficiency low-ripple charge pump (CP) circuit is realized in a 0.35-μm CMOS technology with a power supply of 3.3-V. The charge pump exploits a variable frequency modulation control scheme to achieve both smaller output ripple voltages and better power efficiency. The variable-frequency control block is composed of an error amplifier, a compensator and a voltage-controlled ring oscillator (VCO). Through the shunt feedback, the VCO generates an operating frequency proportional to the CP output voltage. The tuning range of the VCO is from 118-kHz to 1-MHz. When the load current is varied from 3-mA to 30-mA, this CP generates output voltages between 5.8-V to 5-V. The simulated power efficiency lies between 80% to 74% and the simulated output ripples 9.1-mV are less than. The employed off-chip flying capacitor and load capacitor are 330-nF and 2.2-μF, respectively.
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