DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS STANDARD CELL LIBRARY

• Main Authors: Shi-Cheng Wei, 魏仕程
• Other Authors: Shu-Chuan Huang
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/pk7s55

碩士 === 大同大學 === 電機工程學系(所) === 102 === More and more research focuses on asynchronous circuit. However, development of asynchronous circuits lag behind synchronous circuits and EDA tools are not mature. Moreover, most of synthesis tools do not support synthesis of asynchronous circuits. Therefore, we employ an asynchronous circuit synthesis tool developed by the research team from Department of Computer Science and Information Engineering in Tatung University. The other problem is standard cell library. Using normal standard cell library causes poor performance, and hazards. Therefore, asynchronous cell library is necessary. In this thesis, asynchronous cell library is designed and implemented under TSMC 0.18μm CMOS 1P6M process. The C-element, a basic cell for asynchronous circuits, and multi-input dynamic NOR are designed and validated with cell-based design flow. From the simulation results, average cell area of NCL_D QFSM is reduced by 23% with the use of transistor-level implementation of C-element. Using our cell library to implement ISCAS85 circuits with NCL_D, NCL_X, and ROC QDI circuits in Design Compiler, the average area of ROC is reduced by 46%, and average area of NCL_X is reduced by 40% compared to NCL_D. For the QDI FSM implementation, the average area of ROC QFSM is reduced by 28%, and the average area of NCL_X QFSM is reduced by 24% compared to NCL_D.