DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS LOW POWER QDI COMBINATIONAL LOGIC USING 1-OF-2/1-OF-4 CODE
碩士 === 大同大學 === 資訊工程學系(所) === 102 === With technology advances in semiconductor, process, temperature and voltage (PVT) variations become significant in deep submicron design. PVT variations cause delay variations and timing closure problems for synchronous designs. An alternative is to use asynchro...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t9tn69 |