DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS LOW POWER QDI COMBINATIONAL LOGIC USING 1-OF-2/1-OF-4 CODE

• Main Authors: An-hao Peng, 彭安豪
• Other Authors: Fu-chiung Cheng
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/t9tn69

碩士 === 大同大學 === 資訊工程學系(所) === 102 === With technology advances in semiconductor, process, temperature and voltage (PVT) variations become significant in deep submicron design. PVT variations cause delay variations and timing closure problems for synchronous designs. An alternative is to use asynchronous design that can robustly adapt to PVT variations and accommodate timing discrepancies. Among asynchronous design styles, QDI (Quasi-Delay-Insensitive) circuits stand out for its robustness to delay variations, requiring their data to be encoded in a delay-insensitive manner such as dual-rail and 1-of-n codes. Dual-rail QDI logical functions are simple to construct, but 1-of-4 encoded ones may offer the possibility of lower power consumption. This thesis designs and implements two set 1-of-4 code logic cell library. A methodology to reduce the hardware logic of dual-rail DIMS structure circuit by using these 1-of-4 code logic cell libraries is then proposed. Two set of circuits (i.e. verifiable benchmark circuits and ISCAS-85) are exploited to carry out hardware cost and energy performance evaluation. The results show that firstly, for cell library, the cost reduction is significant; secondly, for any give logic functions, the cost reduction is significant if 1-of-4 code inputs are allowed to use and marginal if dual-rail interfaces for inputs and outputs have to preserve.