| Summary: | 碩士 === 大同大學 === 資訊工程學系(所) === 102 === Network-on-Chip (NoC) is a hot topic partitially due to MPSoCs appliations. With the advance of 3D TSV technology, NoC technology is moving towards 3D interconnet. Most of the 3D network implementations are synchronous circuits based on mesh architecture. However, 3D Torus architecture, using wraparound lines, may have better performance on packet transfer.
We design and implement three routing algorithms (i.e. XYZ, round Robin and adptive routing algorithms) for asynchronous QDI 3D Torus NoC. Balsa languages, a concurrent CSP like language is used to specify the routers of the 3D Torus QDI NoC and then is implemented and verified in Altera FPGAs. The experimental results show that, firstly, routers based on XYZ algorithm have the lowest cost and fastest operations, due to their simplicity. Secondly, based on a single router with maxmal packet traffic, average throughput of Round Robin/adaptive algorithm is 1.56/2.01 times faster than that of XYZ algorithm. Thirdly, based on 3x3x3 3D Torus NoC with maxmal packet traffic, average throughput of Round Robin/adaptive algorithm is 1.42/1.73 times faster than that of XYZ algorithm.
|
|---|
