| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 102 === In recent years, Poly-Si flash memory is extensively utilized in various portable electronic products. Poly-Si flash memory can be applied to system-on-panel (SOP) and 3D circuit applications because of its characteristics of low cost and low power consumption. In this thesis, the NVM utilizes a two-bit TaN-SiO2-Si3N4-SiO2-Si (TANOS)-type thin-film transistor (TFT), which has shown NVM characteristics and ultrahigh storage density. In poly-Si TANOS flash memory devices with a long channel, 2-bit operation is difficult to achieved by channel hot electron injection (CHEI) programing and band-to-band tunneling-induced hot-hole injection (BTBT-HHI) erasing owing to the grain boundaries. Accordingly, modulated Fowler-Nordheim (MFN) tunneling, which requires no charge acceleration, was performed in poly-Si TANOS flash memory for spatial programming and erasing. In this thesis, we would like to study the LFN in dual-gate (DG) TANOS with multiple nanowire (multi-NW) channel structure under modulate Fowler–Nordheim tunneling program/erase (P/E) operation. In addition, grain boundary trap density (QT) were examined to assist in the analysis of LFN for poly-Si TANOS NVM. In conclusion, through this thesis, we would like to provide DG TANOS-TFT design with strong reference to optimize memory by reducing the impact of LFN, and thus achieve the idealization of SOP.
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