| Summary: | 碩士 === 國立臺北科技大學 === 機電整合研究所 === 102 === In recent years, high-k/metal-gate (HK/MG) stack technique has widely applied in the advanced MOSFETs because of decreasing equivalent oxide thickness (EOT). It also can solve the leakage issue due to continued device scaling down, raising up the drive current. However, few published literatures discussed the nitridation effect of decoupled plasma nitridation (DPN) process and different annealing temperatures on the electrical characteristics and leakage current behaviors of the devices. Therefore, this study focuses on these points to identify and establish their relationships of the devices.
In this work, the tested 28nm sample wafers came from UMC. The hafnium-based gate dielectric with a profile of HfOx/ZrOy/HfOz (HZH) was deposited with atomic layer deposition (ALD) technology. The wafers were then annealed with different annealing temperatures and nitrogen concentrations after ALD process. After stress or alternating experimental temperatures, degradation behaviors of the devices on stress voltage and temperatures was compared.
The experimental results of this work indicated that the pMOSFETs under the 800~1000℃ annealing temperatures with lower than 10% nitrogen concentration has the largest gate leakage probably because of the larger amount of grain generation in oxide layer. The 800~1000℃ annealing temperatures with lower than 10% nitrogen concentration sample has the largest amount of increasing gate leakage. On the other hand, higher measured temperature we used, higher gate leakage and gate induced drain leakage were observed.
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