Ultra-Low Power PB-CAM Parameter Extractor Based on Adiabatic Logic

碩士 === 國立虎尾科技大學 === 電機工程研究所 === 102 === In this master thesis, seven adiabatic types have been researches with TSMC 0.18μm library, where V_in=1.8V, frequency= 1MHz. We have applied the adiabatic logic structure to further reduce the power dissipation of the PBCAM. In traditional CMOS, the power dis...

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Main Authors:	Cheng-Chih Wang, 王丞志
Other Authors:	Chi-Chia Sun
Format:	Others
Language:	en_US
Published:	2014
Online Access:	http://ndltd.ncl.edu.tw/handle/qm5cvm

id	ndltd-TW-102NYPI5441048
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spelling	ndltd-TW-102NYPI54410482019-09-22T03:41:17Z http://ndltd.ncl.edu.tw/handle/qm5cvm Ultra-Low Power PB-CAM Parameter Extractor Based on Adiabatic Logic 基於低功率絕熱邏輯電路應用於可預先計算內容地址記憶體設計與驗證 Cheng-Chih Wang 王丞志碩士國立虎尾科技大學電機工程研究所 102 In this master thesis, seven adiabatic types have been researches with TSMC 0.18μm library, where V_in=1.8V, frequency= 1MHz. We have applied the adiabatic logic structure to further reduce the power dissipation of the PBCAM. In traditional CMOS, the power dissipation mainly occurs in the MOS transistor during input data switching; however, the adiabatic logic circuit takes an opposing direction to suppress the power dissipation to zero. The experimental results show that the Quasi-1n1p based Block-XOR parameter extractor can save 70.7% in power dissipation compared to the CMOS design. Chi-Chia Sun 宋啟嘉 2014 學位論文 ; thesis 52 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立虎尾科技大學 === 電機工程研究所 === 102 === In this master thesis, seven adiabatic types have been researches with TSMC 0.18μm library, where V_in=1.8V, frequency= 1MHz. We have applied the adiabatic logic structure to further reduce the power dissipation of the PBCAM. In traditional CMOS, the power dissipation mainly occurs in the MOS transistor during input data switching; however, the adiabatic logic circuit takes an opposing direction to suppress the power dissipation to zero. The experimental results show that the Quasi-1n1p based Block-XOR parameter extractor can save 70.7% in power dissipation compared to the CMOS design.
author2	Chi-Chia Sun
author_facet	Chi-Chia Sun Cheng-Chih Wang 王丞志
author	Cheng-Chih Wang 王丞志
spellingShingle	Cheng-Chih Wang 王丞志 Ultra-Low Power PB-CAM Parameter Extractor Based on Adiabatic Logic
author_sort	Cheng-Chih Wang
title	Ultra-Low Power PB-CAM Parameter Extractor Based on Adiabatic Logic
title_short	Ultra-Low Power PB-CAM Parameter Extractor Based on Adiabatic Logic
title_full	Ultra-Low Power PB-CAM Parameter Extractor Based on Adiabatic Logic
title_fullStr	Ultra-Low Power PB-CAM Parameter Extractor Based on Adiabatic Logic
title_full_unstemmed	Ultra-Low Power PB-CAM Parameter Extractor Based on Adiabatic Logic
title_sort	ultra-low power pb-cam parameter extractor based on adiabatic logic
publishDate	2014
url	http://ndltd.ncl.edu.tw/handle/qm5cvm
work_keys_str_mv	AT chengchihwang ultralowpowerpbcamparameterextractorbasedonadiabaticlogic AT wángchéngzhì ultralowpowerpbcamparameterextractorbasedonadiabaticlogic AT chengchihwang jīyúdīgōnglǜjuérèluójídiànlùyīngyòngyúkěyùxiānjìsuànnèiróngdezhǐjìyìtǐshèjìyǔyànzhèng AT wángchéngzhì jīyúdīgōnglǜjuérèluójídiànlùyīngyòngyúkěyùxiānjìsuànnèiróngdezhǐjìyìtǐshèjìyǔyànzhèng
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Ultra-Low Power PB-CAM Parameter Extractor Based on Adiabatic Logic

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