The Design and Implementation of Cyclic Analog-to-Digital Converter

• Main Authors: Che-Yu Chou, 周哲瑀
• Other Authors: Chi-Chang Lu
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/q287xr

碩士 === 國立虎尾科技大學 === 電機工程研究所 === 102 === In recent years, the portability systems become popular. It makes the demand for low voltage and low power circuit increased, such as sensor devices and bio-medical applications. The aim of this thesis is to investigate the design techniques of 10-bit Cyclic ADC for low voltage and low power applications. The target architecture is an Cyclic ADC with the double-sampling technique. The Cyclic ADC consists of the sample-and-hold circuit, sub-ADCs, sub-DACs, decoders, clock generator and multiplexers. In this research, the Cyclic ADC with double-sampling technique has been designed in standard TSMC 0.35um CMOS 2P4M process. Simulation results show that under the 1.5V power supply and the input range of ±0.5V, and the estimated power dissipation is about 8.6mW.