| Summary: | 碩士 === 國立虎尾科技大學 === 電機工程研究所 === 102 === Typical signal processing need to convert analog signals into digital signals for analysis, so the design analog-to-digital converter is an extremely important part of the mixed-signal system. In this paper, use successive approximation register architecture to design circuits for excellent balance between the power consumption and conversion accuracy. The entire circuit consists of sample-and-hold circuit, comparator, digital-to-analog converter, clock generator, and successive approximation register. Sample-and-hold circuit using bootstraped switch to improve on-resistance and linearity. DAC structure is based on binary-weighted capacitor array for MSB part and C-2C capacitor array for LSB part. Furthermore, dual sampling technique is also applied to DAC structure. This scheme provides low power consumption for the proposed SAR ADC.
In this research, 10-bits 727kS/s SAR ADC under a single 1.8V power supply has been designed and simulated in TSMC 0.18μm CMOS 1P6M process. Simulation results show that SAR ADC can operate at an input frequency of 13.5kHz with SFDR of 38.73dB and SNDR of
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37.69dB. The peak DNL is -0.71LSB ~ 0.96 LSB, the peak INL is -1.22LSB ~ 1.49LSB, and the power dissipation is about 150.83μW, the layout area is 0.217135×0.26828mm2. The circuit architecture simulation results are compared with the conventional architecture, to verify the practicality and advantages of this technology, especially to reduce the overall chip area and power consumption.
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