Safe Driving Monitoring System

• Main Authors: Chong-Wei Li, 李崇瑋
• Other Authors: Jui-Cheng Yen
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/17609245992829629436

碩士 === 國立聯合大學 === 電子工程學系碩士班 === 102 === The study proposes a new safe driving monitoring system. The system consists of the monitoring subsystem for movement of driver’s head and the monitoring subsystem for lane departure. It monitors whether the driver’s head and traffic lanes are in normal position. If either abnormal movement of driver’s head or departure of traffic lanes are detected, the system issues a warning signal to the driver immedeiately. In the monitoring subsystem for movement of driver’s head, the LED auxiliary device is adhered to the back cushion behind the driver’s head. The CMOS sensor is used to acquire frames including the region around the driver’s head. The acquired frame is analyzed by the proposed head movement monitoring algorithm. By monitoring the change of the LED region, the algorithm can detect the condition of abnormal head movement. The demonstration of software simulation on the test video indicates the subsystem can detect the abnormal movement of the driver’s head successfully. For hardware verification of the subsystem, the simulation result shows that the throughput can be higher than 15 fps with the hardware cost of 569 logic elements. It reveals that the proposed design achieves the requirement of real time processing. In the monitoring subsystem for lane departure, the CMOS sensor placed at the middle of upper side of windscreen acquires the frames including the road surface in front of the car. The acquired frames are analysed by the proposed lane departure monitoring algorithm. By monitoring the angles variation of marking lane, the algorithm can detect the condition of lane departure. The demonstrations of software simulation on six test videos from different environments indicate the subsystem can detect lane departure successfully. For hardware verification of the subsystem, the simulation results show that the throughput reaches 15 fps with the hardware cost of 43856 logic elements and memory cost of 842496 bit. It reveals that the proposed design fulfils the requirement of real applications.