A Field Programmable Gate Array Time-to-Digital Converter Based on Multiple Counters
碩士 === 國立臺灣科技大學 === 電子工程系 === 102 === A process-voltage-temperature (PVT) insensitive time-to-digital converter (TDC) realized with Field Programmable Gate Array (FPGA) is presented. The proposed TDC is aimed to provide a PVT-insensitive solution with high resolution and wide measurement range. Wit...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87005136987460969554 |
| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 102 === A process-voltage-temperature (PVT) insensitive time-to-digital converter (TDC) realized with Field Programmable Gate Array (FPGA) is presented. The proposed TDC is aimed to provide a PVT-insensitive solution with high resolution and wide measurement range. With the aid of the phase locked loop (PLL) in the FPGA which provides 8 different clock phases, a resolution of about 58.3 ps can be achieved against PVT variations. The proposed TDC successfully eliminates the offset with a simple offset cancellation technique. The short-term measurement result for the differential nonlinearity (DNL) of this TDC is -0.36 ~ 0.41 LSB and the integral nonlinearity (INL) is -0.28 ~ 0.23 LSB. This TDC was tested to be fully functional over 0?aC to 60?aC ambient temperature range with extremely low resolution variations.
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