| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 102 === Multi-Input Multi-Output (MIMO) wireless communication system has been widely recognized as a means of increasing data rates as well as improving transmission quality. However, the advantages provided through MIMO communications come along with prominent drawbacks of enormous system complexity. In order to reduce the complexity of MIMO receiver while still maintaining high data rate and low Bit Error Rate, this thesis presents the design and implementation of a novel architecture of Configurable Joint Detection and Decoding (CJDD). Compared with the conventional separate Detection and Decoding (SDD) scheme, the proposed CJDD architecture integrates the MIMO detector unit and Channel Decoder module into a single block such that a significantly improved BER can be ahievied with comparable hardware complexity. Moreover, the CJDD architecture proposed in this thesis can be operating under various combinations of system configurations as as code rates as well as modulation schemes. Therefore, the CJDD system can be deployed fullfilling the requirements of modern MIMO communication system like LTE, LTE-A, and 802.11n/802.11ac. Specifically, the CJDD engine is designed to support (1) 16QAM + 1/2RATE, (2) 16QAM + 1/3RATE, (3) 64QAM + 1/2RATE, and (4) 64QAM + 1/3RATE. Compared with separate Detection and Decoding, the required signal to noise ratio (SNR) can be reduced about 1.5 ~ 6 dB targeting at a BER of 10-5. In addition, the proposed design was synthesized with TSMC 40nm CMOS technology at 833-MHz clock frequency. An average throughput of 213.6 Mbps ~ 357.6 Mbps with area equivalent to 707.4 Kgates can be achieved.
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