Design of integrated back-contact solar cells using standard CMOS processes

• Main Authors: Tsung-Yen Chuang, 莊宗諺
• Other Authors: San-Liang Lee
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/93718456827497290929

碩士 === 國立臺灣科技大學 === 電子工程系 === 102 === In this thesis, we utilize high resolution doping and multi-layer interconnections provided by standard bulk CMOS processes to implement integrated back-contact solar cells. The diode behavior is realized by parallelly connecting two-dimensional N-well/P-substrate junctions. All heavily-doped contacts are electrically isolated with embedded field oxide in lateral directions to avoid current leakage. The layout of photovoltaic devices within the industry standard electronic design tools is required for the foundry to accept the design for fabrication. Because the processing conditions are optimized for specific design parameters, compliance of the geometric rules is mandatory. Since the on-wafer processing is shared with other customers, as-realized solar cells could be integrated with other microelectronic devices to achieve self-powered system. The main roadblocks of CMOS solar cells include its thick substrate, high substrate resistivity, and poor carrier lifetime. Under near-infrared (980 nm) illumination with an intensity of 1 mW/mm2, as-realized CMOS solar cell has a open-circuit voltage of 0.5~0.52 V, a short-circuit current of 0.068~0.07 mA/mm2, and a conversion efficiency of only 4%. Therefore, this device could generate a electrical power of 0.04 mW/mm2. By thinning down the substrate to tens of micrometers, this device could increase its open-circuit voltage and short-circuit current to 0.54~0.56 V and 0.25~0.27 mA/mm2, respectively, leading to a conversion efficiency of 12~16% and a generated power of 0.16 mW/mm2. Thinned solar cells have similar filling factor of 0.7~0.85 as original ones.