| Summary: | 碩士 === 國立臺灣科技大學 === 色彩與照明科技研究所 === 102 === This paper analyze light extraction efficiency (LEE) and color spatial uniformity (CSU) for flip-chip white light-emitting diodes with chip scale packaging. Depends on the type of package, we propose eight different structures which can be realized. Furthermore, the internal phosphor and silicone structures as well as the external packaging size is optimized. At the same time, the root cause of affect LEE and CSU is discussed. In addition, to ensure the simulation results is close to reality, this study take into account the diffuse reflection characteristics on the surface of the heat sink.
According to the simulation results, we can figure out that the main impact of CSU is phosphor structure and scale of package size. For example, when the height-width-ratio (HWR) of Type I and Type II is from 1.1 to 1.3, the CSU will be reduce them to less than 0.004 within 80 degrees. Besides, when the size of package is 25 times larger than the size of chip, the optimized LEE can be obtained. Among of these, the reflectivity of bottom surface also is the major cause of LEE reduction, including reflective mirror layer of flip-chip and white paint layer of the package. If we could increase the reflectance of these layers, the LEE will be enhanced about 10 to 20% and the CSU won’t be influenced. Finally, in order to further improve the CSU, the different concentrations of nanoparticle doped in different position of the package is analyzed.. From the simulation results, for Type I, we can find that when the concentration is up to 5%, the average CSU can be reduced to 0.00064, and all are less than 0.001 within 80 degrees.
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