High resolution Centered Digital Pulse Width Modulator

• Main Authors: Jing – Hsien Fu, 傅錦憲
• Other Authors: Yi-Jan Chen
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/02966569377888657820

碩士 === 國立臺灣大學 === 電子工程學研究所 === 102 === With the advance of science and technology, the significant developments on mobile phone applications lead the prosperous growth of grobal e-commerce. Since connection requires high quality nowadays, the transmitter in mobile system needs better performance. Centered digital pulse width modulator (Centered DPWM) that is applied to class E PA in polar transmitter of cell phone, needs to provide high frequency and high resolution output pulse gradually. This thesis presents a new centered DPWM architecture. First, this thsis proposes phase generation circuit, which can generate 64 + 8 phases. Then phase combination circuit combines all of these phases to generate 512 phases. PWM signal can be made flexible by these circuits’ co-operation. Phase generation circuit is composed of delay-locked loop (DLL) and phase slicer circuit (PS circuit). Phase combination circuit is composed of segmented replica delay line, MUX and digital control path. The first part of this thesis proposed a 150MHz 6-bit centered DPWM using TSMC 90-nm CMOS process, and this circuit can generates centered pulse width modulation signal. The width per LSB of this circuit is 104ps. INL is 0.12 ~ -0.15 LSB, and DNL is 0.16 ~ -0.1 LSB in simulation. FOM is 1.15 pJ per bit. The second part of this thesis proposed a 30MHz 9-bit centered DPWM using TSMC 90-nm CMOS process, and this circuit can generates dual-phase pulse-width modulation signal. The width per LSB of this circuit is 65ps. INL is measured to be ±0.43 LSB. DNL is measured to be±0.45 LSB. FOM is 1.6 pJ per bit.