The Integration of High Efficiency PWM DC-DC Buck Converter with Low Ripple LDO Regulator

• Main Authors: Ming-Hui, Wei, 魏明輝
• Other Authors: Jia-Chuan Lin. Ph.D.
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/71923914296066863993

碩士 === 國立臺北大學 === 電機工程學系 === 102 === This paper presents a high-efficiency, low electromagnetic interference DC-DC buck switching regulator with low-ripple output. Using spread-spectrum technique, integration of PWM signal reduces the average dispersion of the fundamental frequency, thereby reducing the electromagnetic effects (EMI) in the circuit. With an input voltage range of 3V to 5V, the output voltage after the PWM voltage regulator circuit is 1.5V while the regulated low-ripple output for the LDO is 1.2V. Moreover, it can provide load current of 5mA to 300mA. It also includes a soft start circuit to prevent current surge at startup. This research uses Taiwan Semiconductor Manufacturing Company(TSMC)－0.35 μm 2P4M CMOS process. The overall conversion efficiency is about 75% ,and the total chip layout area is 1.918× 1.918 mm2.