TDC Digital Time Discrimination Technology for Positron Emission Tomography

• Main Authors: Lai, Bao-Ren, 賴寶仁
• Other Authors: Wu, Tzong-Dar
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/cyvh56

碩士 === 國立臺灣海洋大學 === 電機工程學系 === 102 === In this thesis, TDC(time-to-digital converter, TDC) digital time logic circuit implemented in Altera’s Stratix II EP2S60F1020C3 FPGA chip has been proposed. It could measure delay time between positive edges of input pulse and internal clock by using build-in carry adder chain to translate analog delay time into digital signals. The proposed TDC circuit was designed for the time coincidence unit of the PET system. In the TDC location assignment, the lengths of the routs from the pulse input pin to the first adder of carry chain and the clock signal to the D flip-flop have to be kept the same. This design guide could avoid difference of the delay time before the input pulse and the internal clock signal transport into TDC module. If the length is different, the additional delay time will affect the statistic result. Because of the semiconductor manufacturing issue and the physic arrangement in the FPGA, the build-in adders will have different transport delay time. In this restriction, the statistic result will have non-uniform distribution. In ideal condition, every adder must have similar counts in a large amount statistic. Therefore, we have to correct the non-uniform statistic result in order to get a uniform statistic result. In this thesis, we could improve the non-uniform statistic result after the correcting calibration process. Without the correcting process, the original timemark range is only 232 and the time resolution of the TDC is 325.33 ps. After correcting, the timemark range could be extended to 292 and the time resolution is improved to 183.58 ps. Moreover, improper location of the TDC module in FPGA might increase propagation delay time. Therefore, it could reduce correction complexity if we choose suitable location of the TDC module in FPGA according to the I/O pin of the input pulse and the location of the internal system clock.