| Summary: | 碩士 === 國立清華大學 === 工程與系統科學系 === 102 === This thesis elaborated a design process of SAR ADCs, which discussed the fundamental circuit theorems in SAR ADCs by aspects of time and frequency domains and meanwhile, completing the layout and the design of whole ADC by the circuit simulation tools with an easy intuition. Relative to the conventional SAR ADC, the merged capacitor switching based SAR ADCs are more power efficient. Therefore, the thesis implemented two SAR ADCs which based on the merged capacitor switching algorism, including a 12-bit 100k-S/s synchronous SAR ADC, which contained a simple digital control logic and a low-kickback noise comparator to enhance the ENOB, and a 10-bit 10M-S/s asynchronous SAR ADC, which modifying the dynamic D type Flip-Flop to avoid the error in asynchronous clock generator and also used a low-kickback noise comparator to decrease the possibility of the wrong comparative process.
The input signal range of the 12-bit 100k-S/s synchronous SAR ADC could achieve 95% of 2V_DD. The ENOB at Nyquist rate is 9.68, and the FoM is 62(fJ/Con.-step). Furthermore, the ENOB at lower frequency input of ADCs could all achieve over 9.7. In the other hand, the ENOB of the other chips at Nyquist rate are all above 9.61, which verified the influence of the process variation in those chips is small.
The input signal range of the 10-bit 10M-S/s asynchronous SAR ADCs could also achieve 95% of 2V_DD. After decreasing the sampling rate to 3M-S/s, the ENOB at Nyquist rate is 8.73, and the FoM is 88(fJ/Con.-step). Furthermore, the ENOB at lower frequency input of ADCs could all achieve over 8.64. In the other hand, the ENOB of the different chips at Nyquist rate are all above 8.66, which proved that the reliable and repeatable of these chips is well.
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