A Second-Order Delta-Sigma Modulator for Biomedical Signal Application

碩士 === 國立清華大學 === 電機工程學系 === 102 === In recent years , due to the rapid development of medical technology , human Life is extended . This makes the rapid growth of biomedical electronic market , and also let the needs of the physiological signals measurement systems promoted grad- ually .A high prec...

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Bibliographic Details
Main Authors: Si-Cheng Lin, 林嗣澄
Other Authors: Ta-Shun Chu
Format: Others
Language:zh-TW
Published: 2014
Online Access:http://ndltd.ncl.edu.tw/handle/07316589098856819060
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Summary:碩士 === 國立清華大學 === 電機工程學系 === 102 === In recent years , due to the rapid development of medical technology , human Life is extended . This makes the rapid growth of biomedical electronic market , and also let the needs of the physiological signals measurement systems promoted grad- ually .A high precision analog-to-digital (A/D) converter is an important block in the physiological signals measurement systems ; we generally choose the delta-sigma A/D converter as the main architecture for the data converter . To be matching requ irements for the plan , a delta-sigma modulator which is applied in the bio-sensing system that could handle the signal capturing by the devices is implemented in this thesis . This thesis presents a one-bit second-order discrete-time delta-sigma modulator (DT-ΔΣM) , and to be implemented with TSMC 0.18-μm 1P6M process . By using CIFB architecture make the STF to have better filtering performance at high frequency , and make the modulator to have better stability ; the input stage of the operational amplifier use the rail to rail architecture to raise the reliability of the system and ma- ke the modulator still function work even though the outpu swing of the integrat- or is larger . Also using the CDS technique in the first intergrator stage help to reduce the offset of component mismatches and suppress the 1/f noise . The whole delta- sigma modulator operating at 1.8V supply voltage , with 20KHz signal bandwidth , and oversampling ratio of 256 , the designed modulator achieved signal to noise and distortion ratio(SNDR) of 93.26 dB , equivalent to the effective number of bits (ENOB ) 15.26 bits .The power consumption is 2.732 mW , the figure of merit (FoM) is 1.782 pJ/conv. , and the core chip area is 668 x 278μm2 .